Research and implementation of low-power 6T sram designs using 90nm CMOS technology in cadence virtuosoTác giả:
Research and implementation of low-power 6T sram designs using 90nm CMOS technology in cadence virtuoso: Graduation thesis of Computer engineering technology/ Le Trong Hoang, Tran Nguyen Anh Khoa; Truong Ngoc Son (Advisor). -- Ho Chi Minh City: Ho Chi Minh City University of technology and education, 2024
Call no. : KMT-19 621.397 L433-H678
Design and optimization of approximate adder using advanced CMOS technologyTác giả:
Design and optimization of approximate adder using advanced CMOS technology: Graduation project of Electronics and Communications Engineering Technology/ Luong Ngoc Phuong Quynh, Nguyen Phuc Hung; Pham Van Khoa (Advisor)--Ho Chi Minh City: Ho Chi Minh City University of Technology and Education, 2024
Call no.: KĐĐ-41 621.3815 L964-Q178
A Soft Error Tolerant SRAM Design in 130NM CMOS Technology
Soft error is a great concern for microelectronics circuits today. With the advanced development i n CMOS technologies, VLSI circuits are becoming more sensitive to external noise sources, especially radiation particle strikes, which are the cause of soft error. Soft errors are random and do not cause the permanent failure. However, it causes the corruption of stored information, which could turn to the failure in functionality of the circuits.