Research and implementation of low-power 6T sram designs using 90nm CMOS technology in cadence virtuoso

Research and implementation of low-power 6T sram designs using 90nm CMOS technology in cadence virtuoso: Graduation thesis of Computer engineering technology/ Le Trong Hoang, Tran Nguyen Anh Khoa; Truong Ngoc Son (Advisor). -- Ho Chi Minh City: Ho Chi Minh City University of technology and education, 2024 Call no. : KMT-19 621.397 L433-H678