Evaluation of Performance of clock gating techniques in digital circuit designTác giả:
Evaluation of Performance of clock gating techniques in digital circuit design: Graduation Project of Computer Engineering Technology/ Khuu Hoang Duy, Truong Van Ty; Do Duy Tan (Advisor)--Ho Chi Minh City: Ho Chi Minh City University of Technology and Education, 2023
Call no.: KTM-19 681.1 K45-D988
Low power sram with MT-Cmos and gating techniquesTác giả: Do Duy Tan, Ngo Duy Loc, Nguyen Hieu Minh
Low power sram with MT-Cmos and gating techniques. Graduation Project major computer engineering technology. Advisor: Do Duy Tan. Students: Ngo Duy Loc, Nguyen Hieu Minh. Ho Chi Minh City University of Technology and Education, 2025
